The present invention relates to semiconductor memories and a voltage regulator for a bit line of a semiconductor memory cell.
Semiconductor memories usually consist of a matrix of semiconductor memory cells. Each cell is adapted to be controlled separately via a word line and a bit line.
As memory cells, flash memory cells or EEPROM memory cells could be employed in particular. The term EEPROM is an English abbreviation of “Electrically Erasable Programmable Read-Only Memory”. It is a non-volatile memory, i.e. the memory information is maintained even if the memory is not supplied with energy. The memory content can be programmed by electric pulses.
The memory cell of an EEPROM consists of a field effect transistor having a floating gate. The floating gate is a conductor piece above the source drain channel of the EEPROM. The floating gate is electrically isolated from its surrounding, so that charges available on the floating gate cannot flow off readily. The programming of the memory cell is performed in that charges are applied on the floating gate or removed from the floating gate.
The charge available on the floating gate generates a threshold voltage shift of the memory transistor, i.e. the conductivity between the source and the drain is influenced by the floating gate. For reading out the memory information, the current flowing through the memory transistor is ultimately measured. To this end, a constant voltage is applied to the bit line of the memory cell which is connected with the drain. The source of the EEPROM is grounded. Subsequently, the current flowing from the drain to the source is measured. The current intensity measured is a measurement of the charge state of the memory cell.
Voltage regulators are used to charge, during the reading out of the EEPROM, the voltage on the bit line to a set point, and to keep the charge on the set point. FIG. 1 illustrates a conventional voltage regulator used for the reading out of semiconductor memory cells. First of all, the memory cell to be read out is chosen from the memory matrix and connected through to an input 10 of the voltage regulator. The circuit diagram of FIG. 1 illustrates a NOR gate 20. The NOR gate includes two inputs 30 and 40. The first input 30 of the NOR gate 20 is connected to the input of the voltage regulator. The bit line of the memory cell and the input 30 are connected with each other. The voltage regulator of FIG. 1 thus is to provide a predetermined potential on the line 10.
The second input 40 merely serves to switch the voltage regulator on or off. In the on-state, the input is on a low voltage level, so that the NOR gate 30 operates as an inverter with respect to the input 30 and the output 50. An inverter or not-gate is a gate with an input and an output, which fulfills the logic function “not” or “negation”, respectively. A logic “One” at the input becomes a logic “Zero” at the output of the inverter, and vice versa. Two voltage levels correspond to the logic “One” and “Zero”. The inverter supplies an increased output voltage (high level) if no voltage is present at the input. Vice versa, in the case of an increased voltage at the input 30, a low output voltage (low level) is provided by the inverter 20. The characteristic curve of the inverter thus corresponds to a process.
The output 50 of the NOR gate 20 is fed back to the input 30 via a feedback transistor 70. The transistor 70 includes a gate G that is connected with the output 50. The source S of the transistor 70 is connected with the input 30 of the NOR gate 20. The feedback finally provides for the voltage at the NOR gate 30 to be regulated to a particular value.
The NOR gate is connected through by means of the input 40, so that the input 30 and the output 50 act as inverters. FIG. 2a illustrates the section of FIG. 1 that will be discussed in the following. Instead of the NOR gate 20, an inverter 90 is illustrated. Otherwise, the circuit illustrated in FIG. 2a is equal to that of FIG. 1. FIG. 2b illustrates a coordinate system in which the input voltage Ue at the input 30 of the inverter 90 is plotted against the output voltage Ua at the output 50 of the inverter. The characteristic curve 100 of the inverter 90 has a cascaded progression. In the case of a low input voltage Ue, a high output voltage Ua is output. Vice versa, the output voltage Ua is low if the input voltage is high.
If the output 50 of the inverter 90 were directly connected with the input, the inverter 90 would have to exhibit at the operating point the same voltage at the input 30 and at the output 50.
FIG. 2b illustrates the bisecting line 110 of the ordinate and the abscissa of the coordinate system. Each point on the bisecting line 110 therefore has the same voltage Ua and Ue. The intersection of the bisecting line 110 with the characteristic curve 100 indicates the switch point 120 that materializes in the case of a direct feedback. At the input and at the output of the inverter the voltage Us would be present.
The fed-back inverter adjusts itself to its switching threshold. The progression of the characteristic curve in the region of the switch point 120 is substantially linear. As soon as the input voltage Ue is larger than the switch point Us, a voltage that is smaller than Us is generated at the output 50, and vice versa. Due to the negative feedback, the input 30 is thus again shifted in the direction of Us.
The transistor 70 illustrated in FIGS. 1 and 2a effects in balance a voltage difference between the output voltage Ua and the input voltage Ue. The operating point of the fed-back inverter circuit is thus shifted by the gate-source-voltage in the direction along the ordinate. Reference sign 115 illustrates a parallel line to the bisecting line which has been shifted along the ordinate by the voltage difference. Thus, there results the corresponding operating point 125 in FIG. 2b. The output voltage at the operating is Ue+Uth+ΔU. Uth is the threshold voltage of the transistor 70; ΔU is the overdrive voltage of the transistor 70. The overdrive voltage+ΔU is very small vis-à-vis the threshold voltage Uth, so that there applies approximately Uth≈Uth+ΔU. The gate current of the transistor 70 is negligible. The transistor 70 thus prevents current to be fed into the line 30 through the output 50 of the inverter. The current intensity on line 30 is to remain unaltered since it carries the bit line current that is ultimately to be measured. The feedback transistor has a voltage-stabilizing effect. If the voltage at the input 30 of the inverter 90 decreases, the voltage at the output 50 of the inverter increases. Thus, the gate-source-voltage at the transistor 70 increases, so that the source current is increased. Charge carriers are increasingly added to the input 30, so that the potential thereof increases. In the case of a voltage increase at the input 30, the voltage at the output 50 of the inverter decreases. Thus, the gate-source-voltage at the transistor 70 decreases, so that the source current is reduced. If the gate-source-voltage at the transistor 70 underruns the threshold voltage, no more current is supplied to the bit line.
The bit line is thus regulated by the feedback transistor 70 as a source follower to a voltage level that depends on the characteristic curve of the NOR gate 20 or of the corresponding inverter 90, respectively. The signal on line 85 is then further processed for evaluation of the current through the bit line. The evaluation of the memory state is performed by a voltage or current comparison.
The disadvantage of the prior art voltage regulator described is the strong dependency of the bit line voltage on the transistor dimensions in the NOR gate. It is in particular fluctuating process parameters that influence the characteristic curve progression of the NOR gate, so that the operating point is shifted. Furthermore, the bit line voltage depends on the operating voltage VDD since the switch point 120 of the NOR gate in FIG. 1 is also shifted. The higher the operating voltage VDD, the higher becomes the bit line voltage. Last but not least, temperature fluctuations have a strong influence on the input voltage at the input 30 of the NOR gate 20 or of the inverter 90, respectively.
For these and other reasons, there is a need for the present invention.